1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device having a circuit for outputting a boosted potential.
2. Description of the Background Art
Semiconductor memory devices such as a DRAM are provided with a boosted potential generating circuit for supplying a boosted potential, e.g., to word lines.
FIG. 11 is a block diagram showing a structure of a boosted potential generating circuit in a conventional semiconductor memory device. Referring to FIG. 11, the boosted potential generating circuit includes an oscillating circuit 10, a level determining circuit 30, an oscillating circuit 40, a charge pump 50 and a boosted potential node 100.
Oscillating circuit 10 performs oscillation to produce a pulse signal S11 having a first predetermined cycle. Level determining circuit 30 receives pulse signal S11, a potential Vpp of boosted potential node 100 and a reference potential Vref. Reference potential Vref is supplied from a predetermined potential generating circuit (not shown).
Level determining circuit 30 makes comparison between potential Vpp and reference potential Vref in accordance with a cycle defined by pulse signal S11. As a result of the comparison, level determining circuit 30 determines a relative level (i.e., high or low) of potential Vpp with respect to reference potential Vref, and outputs a signal S12 indicative of the result of determination. Level determining circuit 30 determines the level of potential Vpp in response to a fall of pulse signal S11.
Oscillating circuit 40 receives signal S12 and performs oscillation to produce a pulse signal S13 having a predetermined second cycle in response to signal S12. Charge pump 50 receives pulse signal S13. Charge pump 50 is driven in response to pulse signal S13 to supply electric charges to boosted potential node 100. A boosted potential is supplied from boosted potential node 100.
Operation of the boosted potential generating circuit in FIG. 11 will be described below.
FIG. 12 is a timing chart showing signals of various portions of the boosted potential generating circuit in FIG. 11 during operation. In FIG. 12, there are shown potential Vpp and pulse signals S11, S12 and S13.
At time t11 in FIG. 12, the level of potential Vpp lowers below reference potential Vref due to leak of the current or the like. At a subsequent time t12 for the level determination, level determining circuit 30 determines that potential Vpp is lower than reference potential Vref.
Thereby, signal S12 sent from level determining circuit 30 attains the H-level. The H-level of signal S12 means the result of determination that potential Vpp is lower than reference potential Vref.
In response to the H-level of signal S12, oscillating circuit 40 starts oscillation of pulse signal S13. Thereby, charge pump 50 starts the operation. Owing to the operation of charge pump 50, the level of potential Vpp of boosted potential node 100 rises in stepwise fashion.
At time t13, potential Vpp exceeds reference potential Vref. Signal S12 sent from level determining circuit 30 is held at the H-level until next level determination starts at time t14. Therefore, charge pump 50 continues its operation until the start of next level determination.
In the conventional boosted potential generating circuit stated above, charge pump 50, which was once operated, will not stop its operation until the next determination timing even, if the potential Vpp is restored to or above reference potential Vref during the determination cycle. Thus, charge pump 50 operates wastefully. Therefore, such problems arise in the conventional boosted potential generating circuit that overshoot of potential Vpp of the boosted potential node may occur and the power consumption is large.